Place & Route TRACE Report

Loading design for application trce from file counter_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LFXP2-5E
Package:     TQFP144
Performance: 5
Loading device for application trce from file 'mg5a26x29.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.42.
Performance Hardware Data Status:   Final          Version 11.5.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Fri Apr 29 17:40:50 2022

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o Counter_impl1.twr -gui -msgset C:/Users/Dayalan Nair/Desktop/UCT-FPGA-Course-2022/dnair_practicals/Counter/promote.xml Counter_impl1.ncd Counter_impl1.prf 
Design file:     counter_impl1.ncd
Preference file: counter_impl1.prf
Device,speed:    LFXP2-5E,5
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

Preference Summary

  • FREQUENCY PORT "ipClk" 50.000000 MHz (0 errors)
  • 4096 items scored, 0 timing errors detected. Report: 107.701MHz is the maximum frequency for this preference.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_rxio" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_opTxio" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxSend" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rst" (0 errors)
  • 1 item scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opTxBusy" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxValid" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_rxio" (0 errors)
  • 1 item scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_opTxio" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxSend" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
  • 1 item scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" (0 errors)
  • 1 item scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rst" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opTxBusy" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxValid" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "ipClk" 50.000000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 10.715ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UART_Inst/clk_cnt[2] (from ipClk_c +) Destination: FF Data in UART_Inst_opTxio (to ipClk_c +) Delay: 9.338ns (15.2% logic, 84.8% route), 5 logic levels. Constraint Details: 9.338ns physical path delay UART_Inst/SLICE_17 to opUART_Tx_MGIOL meets 20.000ns delay constraint less -0.161ns skew and 0.108ns ONEG0_SET requirement (totaling 20.053ns) by 10.715ns IOL_T28B attributes: FINE=FDEL0 Physical Path Details: Data path UART_Inst/SLICE_17 to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R12C7B.CLK to R12C7B.Q1 UART_Inst/SLICE_17 (from ipClk_c) ROUTE 3 1.598 R12C7B.Q1 to R12C9D.B0 reveal_ist_31 CTOF_DEL --- 0.260 R12C9D.B0 to R12C9D.F0 UART_Inst/SLICE_451 ROUTE 1 0.832 R12C9D.F0 to R12C8D.C1 UART_Inst/un1_tx_state_3_0_o2_5 CTOF_DEL --- 0.260 R12C8D.C1 to R12C8D.F1 UART_Inst/SLICE_352 ROUTE 8 1.217 R12C8D.F1 to R14C7A.A1 UART_Inst/un1_tx_state_3_0_o2 CTOF_DEL --- 0.260 R14C7A.A1 to R14C7A.F1 UART_Inst/SLICE_90 ROUTE 4 1.264 R14C7A.F1 to R15C8D.B0 UART_Inst/N_61 CTOF_DEL --- 0.260 R15C8D.B0 to R15C8D.F0 UART_Inst/SLICE_439 ROUTE 1 3.004 R15C8D.F0 to IOL_T28B.ONEG0 UART_Inst.opTx_7_iv_i (to ipClk_c) -------- 9.338 (15.2% logic, 84.8% route), 5 logic levels. Clock Skew Details: Source Clock Path ipClk to UART_Inst/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R12C7B.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 148 1.394 21.PADDI to IOL_T28B.CLK ipClk_c -------- 1.394 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 10.808ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UART_Inst/clk_cnt[9] (from ipClk_c +) Destination: FF Data in UART_Inst_opTxio (to ipClk_c +) Delay: 9.245ns (15.4% logic, 84.6% route), 5 logic levels. Constraint Details: 9.245ns physical path delay UART_Inst/SLICE_13 to opUART_Tx_MGIOL meets 20.000ns delay constraint less -0.161ns skew and 0.108ns ONEG0_SET requirement (totaling 20.053ns) by 10.808ns IOL_T28B attributes: FINE=FDEL0 Physical Path Details: Data path UART_Inst/SLICE_13 to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R12C8C.CLK to R12C8C.Q0 UART_Inst/SLICE_13 (from ipClk_c) ROUTE 3 1.489 R12C8C.Q0 to R12C9D.C1 reveal_ist_17 CTOF_DEL --- 0.260 R12C9D.C1 to R12C9D.F1 UART_Inst/SLICE_451 ROUTE 1 0.848 R12C9D.F1 to R12C8D.A1 UART_Inst/un1_tx_state_3_0_o2_6 CTOF_DEL --- 0.260 R12C8D.A1 to R12C8D.F1 UART_Inst/SLICE_352 ROUTE 8 1.217 R12C8D.F1 to R14C7A.A1 UART_Inst/un1_tx_state_3_0_o2 CTOF_DEL --- 0.260 R14C7A.A1 to R14C7A.F1 UART_Inst/SLICE_90 ROUTE 4 1.264 R14C7A.F1 to R15C8D.B0 UART_Inst/N_61 CTOF_DEL --- 0.260 R15C8D.B0 to R15C8D.F0 UART_Inst/SLICE_439 ROUTE 1 3.004 R15C8D.F0 to IOL_T28B.ONEG0 UART_Inst.opTx_7_iv_i (to ipClk_c) -------- 9.245 (15.4% logic, 84.6% route), 5 logic levels. Clock Skew Details: Source Clock Path ipClk to UART_Inst/SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R12C8C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 148 1.394 21.PADDI to IOL_T28B.CLK ipClk_c -------- 1.394 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 10.816ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UART_Inst/clk_cnt[4] (from ipClk_c +) Destination: FF Data in UART_Inst_opTxio (to ipClk_c +) Delay: 9.237ns (15.4% logic, 84.6% route), 5 logic levels. Constraint Details: 9.237ns physical path delay UART_Inst/SLICE_16 to opUART_Tx_MGIOL meets 20.000ns delay constraint less -0.161ns skew and 0.108ns ONEG0_SET requirement (totaling 20.053ns) by 10.816ns IOL_T28B attributes: FINE=FDEL0 Physical Path Details: Data path UART_Inst/SLICE_16 to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R12C7C.CLK to R12C7C.Q1 UART_Inst/SLICE_16 (from ipClk_c) ROUTE 3 1.497 R12C7C.Q1 to R12C9D.A0 reveal_ist_27 CTOF_DEL --- 0.260 R12C9D.A0 to R12C9D.F0 UART_Inst/SLICE_451 ROUTE 1 0.832 R12C9D.F0 to R12C8D.C1 UART_Inst/un1_tx_state_3_0_o2_5 CTOF_DEL --- 0.260 R12C8D.C1 to R12C8D.F1 UART_Inst/SLICE_352 ROUTE 8 1.217 R12C8D.F1 to R14C7A.A1 UART_Inst/un1_tx_state_3_0_o2 CTOF_DEL --- 0.260 R14C7A.A1 to R14C7A.F1 UART_Inst/SLICE_90 ROUTE 4 1.264 R14C7A.F1 to R15C8D.B0 UART_Inst/N_61 CTOF_DEL --- 0.260 R15C8D.B0 to R15C8D.F0 UART_Inst/SLICE_439 ROUTE 1 3.004 R15C8D.F0 to IOL_T28B.ONEG0 UART_Inst.opTx_7_iv_i (to ipClk_c) -------- 9.237 (15.4% logic, 84.6% route), 5 logic levels. Clock Skew Details: Source Clock Path ipClk to UART_Inst/SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R12C7C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 148 1.394 21.PADDI to IOL_T28B.CLK ipClk_c -------- 1.394 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 10.979ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UART_Inst/clk_cnt[0] (from ipClk_c +) Destination: FF Data in UART_Inst_opTxio (to ipClk_c +) Delay: 9.074ns (15.7% logic, 84.3% route), 5 logic levels. Constraint Details: 9.074ns physical path delay UART_Inst/SLICE_92 to opUART_Tx_MGIOL meets 20.000ns delay constraint less -0.161ns skew and 0.108ns ONEG0_SET requirement (totaling 20.053ns) by 10.979ns IOL_T28B attributes: FINE=FDEL0 Physical Path Details: Data path UART_Inst/SLICE_92 to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R12C6B.CLK to R12C6B.Q0 UART_Inst/SLICE_92 (from ipClk_c) ROUTE 4 1.318 R12C6B.Q0 to R12C9D.B1 reveal_ist_35 CTOF_DEL --- 0.260 R12C9D.B1 to R12C9D.F1 UART_Inst/SLICE_451 ROUTE 1 0.848 R12C9D.F1 to R12C8D.A1 UART_Inst/un1_tx_state_3_0_o2_6 CTOF_DEL --- 0.260 R12C8D.A1 to R12C8D.F1 UART_Inst/SLICE_352 ROUTE 8 1.217 R12C8D.F1 to R14C7A.A1 UART_Inst/un1_tx_state_3_0_o2 CTOF_DEL --- 0.260 R14C7A.A1 to R14C7A.F1 UART_Inst/SLICE_90 ROUTE 4 1.264 R14C7A.F1 to R15C8D.B0 UART_Inst/N_61 CTOF_DEL --- 0.260 R15C8D.B0 to R15C8D.F0 UART_Inst/SLICE_439 ROUTE 1 3.004 R15C8D.F0 to IOL_T28B.ONEG0 UART_Inst.opTx_7_iv_i (to ipClk_c) -------- 9.074 (15.7% logic, 84.3% route), 5 logic levels. Clock Skew Details: Source Clock Path ipClk to UART_Inst/SLICE_92: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R12C6B.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 148 1.394 21.PADDI to IOL_T28B.CLK ipClk_c -------- 1.394 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 11.098ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3] (from ipClk_c +) Destination: FF Data in top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13] (to ipClk_c +) FF top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12] Delay: 8.658ns (19.4% logic, 80.6% route), 6 logic levels. Constraint Details: 8.658ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_298 meets 20.000ns delay constraint less 0.000ns skew and 0.244ns CE_SET requirement (totaling 19.756ns) by 11.098ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_298: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R14C19C.CLK to R14C19C.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 (from ipClk_c) ROUTE 4 1.309 R14C19C.Q1 to R12C20D.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3] CTOF_DEL --- 0.260 R12C20D.B1 to R12C20D.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459 ROUTE 1 0.598 R12C20D.F1 to R12C20A.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_1 CTOF_DEL --- 0.260 R12C20A.A0 to R12C20A.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 ROUTE 5 0.852 R12C20A.F0 to R10C18B.D0 top_reveal_coretop_instance/top_la0_inst_0/wen CTOF_DEL --- 0.260 R10C18B.D0 to R10C18B.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361 ROUTE 2 0.583 R10C18B.F0 to R10C18D.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0] CTOF_DEL --- 0.260 R10C18D.C1 to R10C18D.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370 ROUTE 3 1.539 R10C18D.F1 to R2C20C.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78 CTOF_DEL --- 0.260 R2C20C.A0 to R2C20C.F0 SLICE_572 ROUTE 8 2.094 R2C20C.F0 to R6C20C.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa (to ipClk_c) -------- 8.658 (19.4% logic, 80.6% route), 6 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R14C19C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_298: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R6C20C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 11.098ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3] (from ipClk_c +) Destination: FF Data in top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15] (to ipClk_c +) FF top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14] Delay: 8.658ns (19.4% logic, 80.6% route), 6 logic levels. Constraint Details: 8.658ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_299 meets 20.000ns delay constraint less 0.000ns skew and 0.244ns CE_SET requirement (totaling 19.756ns) by 11.098ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_299: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R14C19C.CLK to R14C19C.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 (from ipClk_c) ROUTE 4 1.309 R14C19C.Q1 to R12C20D.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3] CTOF_DEL --- 0.260 R12C20D.B1 to R12C20D.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459 ROUTE 1 0.598 R12C20D.F1 to R12C20A.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_1 CTOF_DEL --- 0.260 R12C20A.A0 to R12C20A.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 ROUTE 5 0.852 R12C20A.F0 to R10C18B.D0 top_reveal_coretop_instance/top_la0_inst_0/wen CTOF_DEL --- 0.260 R10C18B.D0 to R10C18B.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361 ROUTE 2 0.583 R10C18B.F0 to R10C18D.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0] CTOF_DEL --- 0.260 R10C18D.C1 to R10C18D.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370 ROUTE 3 1.539 R10C18D.F1 to R2C20C.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78 CTOF_DEL --- 0.260 R2C20C.A0 to R2C20C.F0 SLICE_572 ROUTE 8 2.094 R2C20C.F0 to R6C20B.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa (to ipClk_c) -------- 8.658 (19.4% logic, 80.6% route), 6 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R14C19C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_299: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R6C20B.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 11.098ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3] (from ipClk_c +) Destination: FF Data in top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11] (to ipClk_c +) FF top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10] Delay: 8.658ns (19.4% logic, 80.6% route), 6 logic levels. Constraint Details: 8.658ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_297 meets 20.000ns delay constraint less 0.000ns skew and 0.244ns CE_SET requirement (totaling 19.756ns) by 11.098ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_297: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R14C19C.CLK to R14C19C.Q1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122 (from ipClk_c) ROUTE 4 1.309 R14C19C.Q1 to R12C20D.B1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3] CTOF_DEL --- 0.260 R12C20D.B1 to R12C20D.F1 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_459 ROUTE 1 0.598 R12C20D.F1 to R12C20A.A0 top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/wen_1 CTOF_DEL --- 0.260 R12C20A.A0 to R12C20A.F0 top_reveal_coretop_instance/top_la0_inst_0/SLICE_345 ROUTE 5 0.852 R12C20A.F0 to R10C18B.D0 top_reveal_coretop_instance/top_la0_inst_0/wen CTOF_DEL --- 0.260 R10C18B.D0 to R10C18B.F0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/SLICE_361 ROUTE 2 0.583 R10C18B.F0 to R10C18D.C1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/wen_te[0] CTOF_DEL --- 0.260 R10C18D.C1 to R10C18D.F1 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_370 ROUTE 3 1.539 R10C18D.F1 to R2C20C.A0 top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/N_78 CTOF_DEL --- 0.260 R2C20C.A0 to R2C20C.F0 SLICE_572 ROUTE 8 2.094 R2C20C.F0 to R6C20A.CE top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val_0_sqmuxa (to ipClk_c) -------- 8.658 (19.4% logic, 80.6% route), 6 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/SLICE_122: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R14C19C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/SLICE_297: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R6C20A.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 11.123ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UART_Inst/clk_cnt[2] (from ipClk_c +) Destination: FF Data in UART_Inst/tx_cnt[3] (to ipClk_c +) Delay: 8.433ns (29.9% logic, 70.1% route), 7 logic levels. Constraint Details: 8.433ns physical path delay UART_Inst/SLICE_17 to UART_Inst/SLICE_89 meets 20.000ns delay constraint less 0.000ns skew and 0.444ns LSR_SET requirement (totaling 19.556ns) by 11.123ns Physical Path Details: Data path UART_Inst/SLICE_17 to UART_Inst/SLICE_89: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R12C7B.CLK to R12C7B.Q1 UART_Inst/SLICE_17 (from ipClk_c) ROUTE 3 1.598 R12C7B.Q1 to R12C9D.B0 reveal_ist_31 CTOF_DEL --- 0.260 R12C9D.B0 to R12C9D.F0 UART_Inst/SLICE_451 ROUTE 1 0.832 R12C9D.F0 to R12C8D.C1 UART_Inst/un1_tx_state_3_0_o2_5 CTOF_DEL --- 0.260 R12C8D.C1 to R12C8D.F1 UART_Inst/SLICE_352 ROUTE 8 1.217 R12C8D.F1 to R14C7A.A1 UART_Inst/un1_tx_state_3_0_o2 CTOF_DEL --- 0.260 R14C7A.A1 to R14C7A.F1 UART_Inst/SLICE_90 ROUTE 4 0.849 R14C7A.F1 to R15C7D.A1 UART_Inst/N_61 CTOF_DEL --- 0.260 R15C7D.A1 to R15C7D.F1 UART_Inst/SLICE_455 ROUTE 4 0.599 R15C7D.F1 to R15C7B.A0 UART_Inst/N_99 C0TOFCO_DE --- 0.790 R15C7B.A0 to R15C7B.FCO UART_Inst/SLICE_5 ROUTE 1 0.000 R15C7B.FCO to R15C7C.FCI UART_Inst/un1_tx_cnt_7_cry_2 FCITOF0_DE --- 0.305 R15C7C.FCI to R15C7C.F0 UART_Inst/SLICE_4 ROUTE 1 0.820 R15C7C.F0 to R16C7C.LSR UART_Inst/un1_tx_cnt_7_s_3_0_S0 (to ipClk_c) -------- 8.433 (29.9% logic, 70.1% route), 7 logic levels. Clock Skew Details: Source Clock Path ipClk to UART_Inst/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R12C7B.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to UART_Inst/SLICE_89: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R16C7C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 11.136ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UART_Inst/clk_cnt[3] (from ipClk_c +) Destination: FF Data in UART_Inst_opTxio (to ipClk_c +) Delay: 8.917ns (16.0% logic, 84.0% route), 5 logic levels. Constraint Details: 8.917ns physical path delay UART_Inst/SLICE_16 to opUART_Tx_MGIOL meets 20.000ns delay constraint less -0.161ns skew and 0.108ns ONEG0_SET requirement (totaling 20.053ns) by 11.136ns IOL_T28B attributes: FINE=FDEL0 Physical Path Details: Data path UART_Inst/SLICE_16 to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R12C7C.CLK to R12C7C.Q0 UART_Inst/SLICE_16 (from ipClk_c) ROUTE 3 1.177 R12C7C.Q0 to R12C9D.D0 reveal_ist_29 CTOF_DEL --- 0.260 R12C9D.D0 to R12C9D.F0 UART_Inst/SLICE_451 ROUTE 1 0.832 R12C9D.F0 to R12C8D.C1 UART_Inst/un1_tx_state_3_0_o2_5 CTOF_DEL --- 0.260 R12C8D.C1 to R12C8D.F1 UART_Inst/SLICE_352 ROUTE 8 1.217 R12C8D.F1 to R14C7A.A1 UART_Inst/un1_tx_state_3_0_o2 CTOF_DEL --- 0.260 R14C7A.A1 to R14C7A.F1 UART_Inst/SLICE_90 ROUTE 4 1.264 R14C7A.F1 to R15C8D.B0 UART_Inst/N_61 CTOF_DEL --- 0.260 R15C8D.B0 to R15C8D.F0 UART_Inst/SLICE_439 ROUTE 1 3.004 R15C8D.F0 to IOL_T28B.ONEG0 UART_Inst.opTx_7_iv_i (to ipClk_c) -------- 8.917 (16.0% logic, 84.0% route), 5 logic levels. Clock Skew Details: Source Clock Path ipClk to UART_Inst/SLICE_16: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R12C7C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to opUART_Tx_MGIOL: Name Fanout Delay (ns) Site Resource ROUTE 148 1.394 21.PADDI to IOL_T28B.CLK ipClk_c -------- 1.394 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 11.216ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UART_Inst/clk_cnt[9] (from ipClk_c +) Destination: FF Data in UART_Inst/tx_cnt[3] (to ipClk_c +) Delay: 8.340ns (30.2% logic, 69.8% route), 7 logic levels. Constraint Details: 8.340ns physical path delay UART_Inst/SLICE_13 to UART_Inst/SLICE_89 meets 20.000ns delay constraint less 0.000ns skew and 0.444ns LSR_SET requirement (totaling 19.556ns) by 11.216ns Physical Path Details: Data path UART_Inst/SLICE_13 to UART_Inst/SLICE_89: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.383 R12C8C.CLK to R12C8C.Q0 UART_Inst/SLICE_13 (from ipClk_c) ROUTE 3 1.489 R12C8C.Q0 to R12C9D.C1 reveal_ist_17 CTOF_DEL --- 0.260 R12C9D.C1 to R12C9D.F1 UART_Inst/SLICE_451 ROUTE 1 0.848 R12C9D.F1 to R12C8D.A1 UART_Inst/un1_tx_state_3_0_o2_6 CTOF_DEL --- 0.260 R12C8D.A1 to R12C8D.F1 UART_Inst/SLICE_352 ROUTE 8 1.217 R12C8D.F1 to R14C7A.A1 UART_Inst/un1_tx_state_3_0_o2 CTOF_DEL --- 0.260 R14C7A.A1 to R14C7A.F1 UART_Inst/SLICE_90 ROUTE 4 0.849 R14C7A.F1 to R15C7D.A1 UART_Inst/N_61 CTOF_DEL --- 0.260 R15C7D.A1 to R15C7D.F1 UART_Inst/SLICE_455 ROUTE 4 0.599 R15C7D.F1 to R15C7B.A0 UART_Inst/N_99 C0TOFCO_DE --- 0.790 R15C7B.A0 to R15C7B.FCO UART_Inst/SLICE_5 ROUTE 1 0.000 R15C7B.FCO to R15C7C.FCI UART_Inst/un1_tx_cnt_7_cry_2 FCITOF0_DE --- 0.305 R15C7C.FCI to R15C7C.F0 UART_Inst/SLICE_4 ROUTE 1 0.820 R15C7C.F0 to R16C7C.LSR UART_Inst/un1_tx_cnt_7_s_3_0_S0 (to ipClk_c) -------- 8.340 (30.2% logic, 69.8% route), 7 logic levels. Clock Skew Details: Source Clock Path ipClk to UART_Inst/SLICE_13: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R12C8C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to UART_Inst/SLICE_89: Name Fanout Delay (ns) Site Resource ROUTE 148 1.233 21.PADDI to R16C7C.CLK ipClk_c -------- 1.233 (0.0% logic, 100.0% route), 0 logic levels. Report: 107.701MHz is the maximum frequency for this preference. ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_rxio" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_opTxio" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxSend" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rst" ; 1 item scored. -------------------------------------------------------------------------------- Blocked: Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Port Pad ipnReset Destination: FF Data in UART_Inst/rst (to ipClk_c +) Delay: 2.108ns (53.0% logic, 47.0% route), 2 logic levels. Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.858 19.PAD to 19.PADDI ipnReset ROUTE 1 0.990 19.PADDI to R11C6C.D0 ipnReset_c CTOF_DEL --- 0.260 R11C6C.D0 to R11C6C.F0 UART_Inst/SLICE_52 ROUTE 1 0.000 R11C6C.F0 to R11C6C.DI0 UART_Inst/ipnReset_c_i (to ipClk_c) -------- 2.108 (53.0% logic, 47.0% route), 2 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opTxBusy" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxValid" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_rxio" ; 1 item scored. -------------------------------------------------------------------------------- Blocked: Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Port Pad ipUART_Rx Destination: FF Data in UART_Inst_rxio (to ipClk_c +) Delay: 0.858ns (100.0% logic, 0.0% route), 1 logic levels. Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.858 110.PAD to 110.PADDI ipUART_Rx ROUTE 3 0.000 110.PADDI to IOL_T28A.DI ipUART_Rx_c (to ipClk_c) -------- 0.858 (100.0% logic, 0.0% route), 1 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_opTxio" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxSend" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" ; 1 item scored. -------------------------------------------------------------------------------- Blocked: Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Port Pad ipUART_Rx Destination: FF Data in top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0] (to ipClk_c +) Delay: 3.521ns (24.4% logic, 75.6% route), 1 logic levels. Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.858 110.PAD to 110.PADDI ipUART_Rx ROUTE 3 2.663 110.PADDI to R14C11C.M0 ipUART_Rx_c (to ipClk_c) -------- 3.521 (24.4% logic, 75.6% route), 1 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" ; 1 item scored. -------------------------------------------------------------------------------- Blocked: Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Port Pad ipUART_Rx Destination: FF Data in top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45] (to ipClk_c +) Delay: 3.216ns (26.7% logic, 73.3% route), 1 logic levels. Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.858 110.PAD to 110.PADDI ipUART_Rx ROUTE 3 2.358 110.PADDI to R14C13B.M1 ipUART_Rx_c (to ipClk_c) -------- 3.216 (26.7% logic, 73.3% route), 1 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rst" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opTxBusy" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxValid" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "ipClk" 50.000000 MHz ; | 50.000 MHz| 107.701 MHz| 5 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: jtaghub16_jtck Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK Loads: 169 No transfer within this clock domain is found Clock Domain: ipClk_c Source: ipClk.PAD Loads: 148 Covered under: FREQUENCY PORT "ipClk" 50.000000 MHz ; Data transfers from: Clock Domain: jtaghub16_jtck Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 5179 paths, 1 nets, and 3613 connections (95.94% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2 Fri Apr 29 17:40:51 2022 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Counter_impl1.twr -gui -msgset C:/Users/Dayalan Nair/Desktop/UCT-FPGA-Course-2022/dnair_practicals/Counter/promote.xml Counter_impl1.ncd Counter_impl1.prf Design file: counter_impl1.ncd Preference file: counter_impl1.prf Device,speed: LFXP2-5E,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY PORT "ipClk" 50.000000 MHz (0 errors)
  • 4096 items scored, 0 timing errors detected.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_rxio" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_opTxio" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxSend" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rst" (0 errors)
  • 1 item scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opTxBusy" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxValid" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_rxio" (0 errors)
  • 1 item scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_opTxio" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxSend" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
  • 1 item scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" (0 errors)
  • 1 item scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rst" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opTxBusy" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxValid" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[8]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[9]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[0]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[1]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[2]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[3]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[4]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[5]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[6]" (0 errors)
  • 0 items scored.
  • BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[7]" (0 errors)
  • 0 items scored. BLOCK ASYNCPATHS BLOCK RESETPATHS BLOCK JTAG PATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "ipClk" 50.000000 MHz ; 4096 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.128ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0(ASIC) (to ipClk_c +) Delay: 0.259ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.259ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_44 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 meets 0.081ns ADDR_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.131ns) by 0.128ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_44 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R11C12C.CLK to R11C12C.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_44 (from ipClk_c) ROUTE 5 0.139 R11C12C.Q0 to *R_R13C11.ADW3 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3] (to ipClk_c) -------- 0.259 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_44: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R11C12C.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to *R_R13C11.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.128ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0(ASIC) (to ipClk_c +) Delay: 0.259ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.259ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_45 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 meets 0.081ns ADDR_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.131ns) by 0.128ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_45 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R11C12B.CLK to R11C12B.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_45 (from ipClk_c) ROUTE 5 0.139 R11C12B.Q1 to *R_R13C11.ADW2 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2] (to ipClk_c) -------- 0.259 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_45: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R11C12B.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to *R_R13C11.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.128ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0(ASIC) (to ipClk_c +) Delay: 0.259ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.259ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_44 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 meets 0.081ns ADDR_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.131ns) by 0.128ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_44 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R11C12C.CLK to R11C12C.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_44 (from ipClk_c) ROUTE 5 0.139 R11C12C.Q1 to *R_R13C11.ADW4 top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4] (to ipClk_c) -------- 0.259 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_44: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R11C12C.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to *R_R13C11.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.130ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1(ASIC) (to ipClk_c +) Delay: 0.277ns (43.3% logic, 56.7% route), 1 logic levels. Constraint Details: 0.277ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_219 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 meets 0.097ns DATA_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.147ns) by 0.130ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_219 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R14C9A.CLK to R14C9A.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_219 (from ipClk_c) ROUTE 1 0.157 R14C9A.Q0 to EBR_R13C8.DI6 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6] (to ipClk_c) -------- 0.277 (43.3% logic, 56.7% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_219: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R14C9A.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to EBR_R13C8.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.130ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1(ASIC) (to ipClk_c +) Delay: 0.277ns (43.3% logic, 56.7% route), 1 logic levels. Constraint Details: 0.277ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_219 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 meets 0.097ns DATA_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.147ns) by 0.130ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_219 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R14C9A.CLK to R14C9A.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_219 (from ipClk_c) ROUTE 1 0.157 R14C9A.Q1 to EBR_R13C8.DI7 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7] (to ipClk_c) -------- 0.277 (43.3% logic, 56.7% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_219: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R14C9A.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to EBR_R13C8.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.133ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1(ASIC) (to ipClk_c +) Delay: 0.280ns (42.9% logic, 57.1% route), 1 logic levels. Constraint Details: 0.280ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_222 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 meets 0.097ns DATA_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.147ns) by 0.133ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_222 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R12C10C.CLK to R12C10C.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_222 (from ipClk_c) ROUTE 1 0.160 R12C10C.Q1 to EBR_R13C8.DI13 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13] (to ipClk_c) -------- 0.280 (42.9% logic, 57.1% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_222: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R12C10C.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to EBR_R13C8.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.193ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0(ASIC) (to ipClk_c +) Delay: 0.340ns (35.3% logic, 64.7% route), 1 logic levels. Constraint Details: 0.340ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_235 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0 meets 0.097ns DATA_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.147ns) by 0.193ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_235 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R16C10C.CLK to R16C10C.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_235 (from ipClk_c) ROUTE 1 0.220 R16C10C.Q0 to EBR_R13C11.DI2 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38] (to ipClk_c) -------- 0.340 (35.3% logic, 64.7% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_235: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R16C10C.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_1_0: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to *R_R13C11.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.197ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1(ASIC) (to ipClk_c +) Delay: 0.344ns (34.9% logic, 65.1% route), 1 logic levels. Constraint Details: 0.344ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_227 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 meets 0.097ns DATA_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.147ns) by 0.197ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_227 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R14C9B.CLK to R14C9B.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_227 (from ipClk_c) ROUTE 1 0.224 R14C9B.Q0 to EBR_R13C8.DI22 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22] (to ipClk_c) -------- 0.344 (34.9% logic, 65.1% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_227: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R14C9B.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to EBR_R13C8.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.197ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1(ASIC) (to ipClk_c +) Delay: 0.344ns (34.9% logic, 65.1% route), 1 logic levels. Constraint Details: 0.344ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_227 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 meets 0.097ns DATA_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.147ns) by 0.197ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_227 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R14C9B.CLK to R14C9B.Q1 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_227 (from ipClk_c) ROUTE 1 0.224 R14C9B.Q1 to EBR_R13C8.DI23 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23] (to ipClk_c) -------- 0.344 (34.9% logic, 65.1% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_227: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R14C9B.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to EBR_R13C8.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.197ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26] (from ipClk_c +) Destination: PDPW16KB Port top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1(ASIC) (to ipClk_c +) Delay: 0.344ns (34.9% logic, 65.1% route), 1 logic levels. Constraint Details: 0.344ns physical path delay top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_229 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1 meets 0.097ns DATA_HLD and 0.000ns delay constraint less -0.050ns skew requirement (totaling 0.147ns) by 0.197ns Physical Path Details: Data path top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_229 to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.120 R14C7B.CLK to R14C7B.Q0 top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_229 (from ipClk_c) ROUTE 1 0.224 R14C7B.Q0 to EBR_R13C8.DI26 top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26] (to ipClk_c) -------- 0.344 (34.9% logic, 65.1% route), 1 logic levels. Clock Skew Details: Source Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/SLICE_229: Name Fanout Delay (ns) Site Resource ROUTE 148 0.300 21.PADDI to R14C7B.CLK ipClk_c -------- 0.300 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path ipClk to top_reveal_coretop_instance/top_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4753247532p132a0a97_0_0_1: Name Fanout Delay (ns) Site Resource ROUTE 148 0.350 21.PADDI to EBR_R13C8.CLKW ipClk_c -------- 0.350 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_rxio" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst_opTxio" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxSend" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_TxData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_state[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/tx_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/txData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_state[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rx_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/rst" ; 1 item scored. -------------------------------------------------------------------------------- Blocked: Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Port Pad ipnReset Destination: FF Data in UART_Inst/rst (to ipClk_c +) Delay: 0.636ns (65.4% logic, 34.6% route), 2 logic levels. Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.557 19.PAD to 19.PADDI ipnReset ROUTE 1 0.301 19.PADDI to R11C6C.D0 ipnReset_c CTOF_DEL --- 0.085 R11C6C.D0 to R11C6C.F0 UART_Inst/SLICE_52 ROUTE 1 0.000 R11C6C.F0 to R11C6C.DI0 UART_Inst/ipnReset_c_i (to ipClk_c) -------- 0.943 (68.1% logic, 31.9% route), 2 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opTxBusy" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxValid" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/opRxData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt2[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipnReset" TO CELL "UART_Inst/clk_cnt[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_rxio" ; 1 item scored. -------------------------------------------------------------------------------- Blocked: Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Port Pad ipUART_Rx Destination: FF Data in UART_Inst_rxio (to ipClk_c +) Delay: 0.357ns (100.0% logic, 0.0% route), 1 logic levels. Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.557 110.PAD to 110.PADDI ipUART_Rx ROUTE 3 0.000 110.PADDI to IOL_T28A.DI ipUART_Rx_c (to ipClk_c) -------- 0.557 (100.0% logic, 0.0% route), 1 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst_opTxio" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxSend" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_TxData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" ; 1 item scored. -------------------------------------------------------------------------------- Blocked: Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Port Pad ipUART_Rx Destination: FF Data in top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0] (to ipClk_c +) Delay: 1.032ns (34.6% logic, 65.4% route), 1 logic levels. Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.557 110.PAD to 110.PADDI ipUART_Rx ROUTE 3 0.850 110.PADDI to R14C11C.M0 ipUART_Rx_c (to ipClk_c) -------- 1.407 (39.6% logic, 60.4% route), 1 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" ; 1 item scored. -------------------------------------------------------------------------------- Blocked: Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Port Pad ipUART_Rx Destination: FF Data in top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45] (to ipClk_c +) Delay: 0.955ns (37.4% logic, 62.6% route), 1 logic levels. Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.557 110.PAD to 110.PADDI ipUART_Rx ROUTE 3 0.759 110.PADDI to R14C13B.M1 ipUART_Rx_c (to ipClk_c) -------- 1.316 (42.3% logic, 57.7% route), 1 logic levels. ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_state[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/tx_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/txData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_state[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rx_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/rst" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opTxBusy" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxValid" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/opRxData[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[8]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt2[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM PORT "ipUART_Rx" TO CELL "UART_Inst/clk_cnt[9]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_rxio" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst_opTxio" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxSend" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_TxData[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_stretch" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[43]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[44]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[45]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_dout[46]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[35]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[36]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[37]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[38]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[39]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[40]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[41]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[42]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[43]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[44]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[45]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/trace_din_d[46]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_d" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/start_bit" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/sample_en_d" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full_reg" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/full" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/force_trig" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/clear" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/capture" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed_p1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/tm_u/armed" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/te_block" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[18]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[43]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[44]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[45]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_tr_dout[46]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[16]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[17]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[19]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/r_w" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_fast" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "top_reveal_coretop_instance/top_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_state[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/tx_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/txData[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_state[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rx_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/rst" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opTxBusy" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxValid" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/opRxData[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[0]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[1]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[2]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[3]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[4]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[5]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[6]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[7]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[8]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt2[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[0]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[1]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[2]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[3]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[4]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[5]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[6]" ; 0 items scored. -------------------------------------------------------------------------------- ================================================================================ Preference: BLOCK PATH FROM CELL "UART_Inst/clk_cnt[9]" TO PORT "opLED[7]" ; 0 items scored. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY PORT "ipClk" 50.000000 MHz ; | -| -| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 2 clocks: Clock Domain: jtaghub16_jtck Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK Loads: 169 No transfer within this clock domain is found Clock Domain: ipClk_c Source: ipClk.PAD Loads: 148 Covered under: FREQUENCY PORT "ipClk" 50.000000 MHz ; Data transfers from: Clock Domain: jtaghub16_jtck Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 5179 paths, 1 nets, and 3613 connections (95.94% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------